Computer Architecture — Concise & Focused Notes

These notes cover fundamental concepts, performance metrics, CPU organization, memory systems, pipelining, ISAs, I/O, multicore systems and practical exam-oriented pointers.

1. Overview

Computer Architecture defines the structure and behavior visible to a programmer — instruction sets, data types, addressing modes, and the programmer-visible resources. Computer Organization refers to implementation details such as control signals, memory technology, and physical components.

2. Central Processing Unit (CPU)

The CPU consists of the arithmetic logic unit (ALU), control unit, registers, and often specialized units (FPUs, vector units). Key parts:

Registers: Fast storage inside CPU (PC, IR, general-purpose registers).
ALU: Performs arithmetic and logic operations.
Control Unit: Decodes instructions and orchestrates datapath.

3. Instruction Set Architecture (ISA)

ISA is the contract between hardware and software. Major ISA characteristics:

RISC vs CISC — RISC: fixed-size, simple instructions; CISC: complex multi-step instructions.
Addressing modes — immediate, direct, indirect, register, indexed.
Endianness — little vs big endian.

4. Microarchitecture & Datapath

The microarchitecture implements the ISA via datapaths and control. Elements include: registers file, ALU, multiplexers, pipeline stages, forwarding paths, control signals.

5. Pipelining

Pipelining increases instruction throughput by overlapping instruction stages (fetch, decode, execute, memory, writeback). Key issues:

Hazards: data hazards (RAW, WAR, WAW), control hazards (branches), structural hazards.
Solutions: forwarding (bypassing), pipeline stalls, branch prediction, delayed branching.
Performance: ideal speedup ≈ pipeline depth (limited by hazards and stalls).

6. Memory Hierarchy

Memory hierarchy organizes storage by speed, cost, and size: registers → caches → main memory → secondary storage. Principles:

Temporal locality and spatial locality guide cache design.
Cache parameters: size, block (line) size, associativity, replacement policy (LRU, FIFO).
Write policies: write-through vs write-back; write-allocate vs no-write-allocate.

7. Virtual Memory

Virtual memory provides an illusion of large contiguous memory using pages, TLBs (translation lookaside buffers), and page tables. Key metrics: page fault rate, TLB hit rate, effective memory access time.

8. I/O and Peripherals

I/O methods: programmed I/O, interrupt-driven I/O, direct memory access (DMA). Buses and controllers coordinate device communication. Performance depends on latency and throughput.

9. Parallelism and Multicore

Parallelism improves performance: instruction-level (ILP), data-level (SIMD/Vector), thread-level (multicore). Challenges: cache coherence, synchronization, Amdahl's law for speedup limits.

10. Performance Metrics

Important metrics:

Clock rate (Hz), CPI (cycles per instruction), IPC (instructions per cycle).
Execution time = (Instruction count) × (CPI) × (Clock cycle time).
Throughput vs latency tradeoffs.

11. Design Considerations & Tradeoffs

Designers balance cost, performance, power, complexity. Example tradeoffs: cache size vs access time, pipeline depth vs branch penalty, superscalar width vs hardware complexity.

12. Quick Exam Tips

Memorize formula: Execution time = IC × CPI × Tcycle.
Practice cache mapping (direct, associative, set-associative) problems and pipeline diagrams with hazards.
Understand TLB/page table translations and effective access time calculations.

50 Practice MCQs

Correct options are highlighted when answers are shown.

Q1. Which component holds the address of the next instruction to be executed?

A. Instruction Register (IR)

B. Program Counter (PC)

C. Stack Pointer (SP)

D. Memory Data Register (MDR)

Q2. In a pipelined CPU, the primary purpose of forwarding (bypassing) is to:

A. Reduce stalls due to data hazards

B. Improve branch prediction accuracy

C. Increase cache hit rate

D. Replace the need for register files

Q3. Which of the following is a measure of average time to service a memory reference including cache hits and misses?

A. CPI

B. Effective Access Time (EAT)

C. Latency Bandwidth Product

D. Throughput

Q4. Which cache mapping uses a hash of the block number to determine the set but allows multiple blocks per set?

A. Direct-mapped

B. Fully associative

C. Set-associative

D. Virtual-mapped

Q5. Write-back cache policy means:

A. Modified data is written to main memory only when it is evicted

B. Every write immediately writes to main memory

C. Write operations are not allowed

D. Cache never modifies data

Q6. The main difference between RISC and CISC is:

A. RISC has simpler instructions and fixed length; CISC has complex variable-length instructions

B. RISC is interpreted, CISC is compiled

C. RISC uses microcode, CISC does not

D. RISC has fewer registers than CISC

Q7. CPI stands for:

A. Cycles per Instruction (average)

B. Cycles Per Instruction

C. Clock Period Interval

D. Compute Performance Index

Q8. Which structure is used to speed up virtual-to-physical address translation?

A. TLB (Translation Lookaside Buffer)

B. Page Table

C. Cache Directory

D. MMU Register File

Q9. Amdahl's Law is used to:

A. Compute theoretical speedup from enhancing a portion of a system

B. Determine cache replacement policy

C. Select branch prediction algorithm

D. Measure power consumption

Q10. Which of the following is a control hazard mitigation technique?

A. Cache blocking

B. Branch prediction

C. Out-of-order commit

D. Register renaming

Q11. In a 5-stage pipeline (IF, ID, EX, MEM, WB), where does memory read/write happen?

A. ID

B. EX

C. MEM

D. WB

Q12. Which technique helps increase ILP by allowing multiple instructions to be issued per cycle?

A. Superscalar execution

B. Pipelining

C. Caching

D. Virtual memory

Q13. Register renaming primarily solves which hazard?

A. RAW

B. WAW and WAR (name) hazards

C. Control hazards

D. Structural hazards

Q14. Which of the following is NOT a type of cache miss?

A. Compulsory

B. Capacity

C. Conflict

D. Latency

Q15. The memory addressing mode where the operand is part of the instruction is called:

A. Immediate addressing

B. Direct addressing

C. Indirect addressing

D. Register addressing

Q16. The process of converting high-level language to machine code that the processor executes is called:

A. Interpretation

B. Linking

C. Compilation

D. Assembly

Q17. A write-through cache:

A. Writes data to both cache and main memory immediately

B. Writes only to cache and delays memory update

C. Never writes to main memory

D. Is only used in virtual memory systems

Q18. Which component translates virtual addresses to physical addresses?

A. MMU

B. Memory Management Unit (MMU)

C. TLB

D. Interrupt Controller

Q19. The term 'latency' in computer architecture commonly refers to:

A. Time taken to complete a single operation

B. Bandwidth over time

C. Number of operations per second

D. Cache size

Q20. Which scheduling mechanism allows devices to transfer data directly to memory without CPU intervention?

A. Interrupt-driven I/O

B. Direct Memory Access (DMA)

C. Polling

D. Programmed I/O

Q21. In a multicore system, cache coherence ensures:

A. All cores see a consistent view of shared memory

B. Each core has identical caches

C. TLBs are shared among cores

D. Memory is always write-through

Q22. The address space provided by a 32-bit processor is:

A. 4 GB

B. 2 GB

C. 8 GB

D. 16 GB

Q23. Which of the following improves performance by reducing branch penalty?

A. Larger caches

B. Branch prediction

C. More registers

D. Virtual memory

Q24. Which pipeline hazard is created when two instructions write the same register in different order?

A. RAW

B. WAW (Write After Write)

C. WAR

D. Structural hazard

Q25. Which replacement policy approximates LRU with low overhead?

A. Random

B. FIFO

C. LRU stack or pseudo-LRU

D. MRU

Q26. Which is true about superscalar processors?

A. They issue multiple instructions per cycle using multiple functional units

B. They execute only one instruction at a time

C. They rely solely on long pipelines

D. They remove the need for caches

Q27. Which of these is NOT part of the memory hierarchy?

A. Registers

B. L1 cache

C. SSD

D. ALU

Q28. The typical page size in many systems is:

A. 32 bytes

B. 256 bytes

C. 4 KB

D. 1 MB

Q29. In an instruction cycle, the phase that decodes the opcode is:

A. Instruction Decode (ID)

B. Instruction Fetch (IF)

C. Execute (EX)

D. Write Back (WB)

Q30. Which component controls data transfers between CPU and memory mapped I/O devices?

A. Cache controller

B. Bus and I/O controller

C. ALU

D. Branch predictor

Q31. SIMD stands for:

A. Single Instruction, Multiple Data

B. Single Instruction, Multiple Devices

C. Simple Instruction, Multiple Data

D. Serial Instruction, Multiple Data

Q32. The operation of splitting tasks across multiple pipeline stages is called:

A. Pipelining

B. Multithreading

C. Superscalar

D. Caching

Q33. Which of the following improves cache hit rate for programs with spatial locality?

A. Larger block (line) size

B. Smaller cache size

C. More TLB entries

D. Out-of-order execution

Q34. A translation lookaside buffer (TLB) miss requires:

A. A page table lookup to get the physical frame

B. A cache flush

C. Branch prediction update

D. Pipeline flush

Q35. Which is a measure of throughput in memory systems?

A. Latency

B. Bandwidth (bytes/sec)

C. CPI

D. Page fault rate

Q36. Which of the following is used to avoid pipeline stalls due to branch instructions?

A. Branch prediction and speculative execution

B. Write-through cache

C. Virtual memory

D. DMA

Q37. The stack pointer (SP) typically points to:

A. The top of the current stack frame

B. The start of program code

C. The base of heap

D. The instruction register

Q38. Which is an example of temporal locality?

A. Repeated access to the same memory location within a short time

B. Accessing sequential array elements once

C. Accessing random memory locations across large arrays

D. Loading a new program

Q39. Which technique reduces register file write hazards by renaming registers to physical ones?

A. Register renaming

B. Out-of-order issue

C. Speculative execution

D. Loop unrolling

Q40. Which of the following storage offers non-volatile, high capacity but higher latency compared to DRAM?

A. Cache

B. SRAM

C. SSD / HDD

D. Registers

Q41. Which of these is true about write-back vs write-through caches?

A. Write-back can reduce memory traffic but needs dirty tracking

B. Write-through always reduces memory traffic

C. Write-back guarantees main memory always updated

D. Write-through never writes to cache

Q42. Which bus arbitration technique allows devices to request the bus and be granted in priority order?

A. Priority arbitration

B. Round-robin only

C. Time-division multiplexing only

D. Direct-mapped arbitration

Q43. Which stage writes results back to register file in a classic 5-stage pipeline?

A. Write Back (WB)

B. Execute (EX)

C. Instruction Fetch (IF)

D. Memory (MEM)

Q44. Which of the following is a characteristic of CISC architectures historically?

A. Complex instructions that may perform multiple low-level operations

B. Only fixed-length instructions

C. Minimal microcode use

D. Lack of addressing modes

Q45. Which mechanism reduces the cost of context switches by allowing multiple threads to share pipeline resources?

A. Hardware multithreading (SMT)

B. Branch prediction

C. Write buffering

D. Cache locking

Q46. Effective Access Time (EAT) in a system with TLB is computed using:

A. Only cache hit time

B. TLB hit rate × (TLB access + memory access) + TLB miss penalty

C. Disk access time

D. Clock cycle time only

Q47. Which of these is NOT a pipeline stall cause?

A. Data hazard

B. Branch misprediction

C. Structural hazard

D. Larger register file size

Q48. Which addressing scheme uses base and offset registers to compute effective address?

A. Base+offset (indexed) addressing

B. Immediate addressing

C. Direct addressing

D. Stack addressing

Q49. A page fault occurs when:

A. The referenced page is not present in physical memory

B. TLB has an entry

C. Cache hit occurs

D. Memory is read-only

Q50. Which technique improves performance by executing instructions out of program order but committing results in program order?

A. Out-of-order execution with reorder buffer

B. In-order superscalar

C. Simple pipelining

D. Vectorization only