Digital Electronics — Concise Notes

These notes are exam-focused and practical. Covering logic fundamentals, combinational & sequential circuits, number systems, ADC/DAC, programmable devices, and timing/logic design techniques.

1. Fundamentals

Digital electronics deals with discrete values (typically binary). Key concepts:

Binary number system, radix, conversions between binary, decimal, hex.
Logic levels: TTL/CMOS voltage thresholds, fan-in/fan-out.
Logic gates: AND, OR, NOT, NAND, NOR, XOR, XNOR — truth tables and boolean expressions.

2. Boolean Algebra & Simplification

Laws: commutative, associative, distributive, De Morgan's theorems. Simplification techniques include algebraic manipulation, Karnaugh maps (K‑maps) for up to 6 variables, and Quine–McCluskey for larger problems.

3. Combinational Circuits

Combinational circuits output depends only on current inputs. Examples:

Adders: half adder, full adder, ripple-carry adder, carry lookahead adder.
Multiplexers, demultiplexers, encoders, decoders, comparators.

4. Sequential Circuits

Sequential circuits depend on inputs and previous states (memory). Key elements:

Flip-flops: SR, JK, D, T. Timing behavior: setup, hold times, propagation delay.
Counters: asynchronous (ripple) and synchronous counters, modulus counters, decade counters.
Registers, shift registers (SISO, SIPO, PISO, PIPO).

5. Number Systems & Codes

Signed numbers: two's complement, sign-magnitude, ones' complement. Common codes: BCD, Gray code, ASCII.

6. Timing & Propagation

Critical timing parameters: propagation delay (t_pd), contamination delay (t_cd), setup time (t_su), hold time (t_h). Timing diagrams are essential for verification.

7. ADC & DAC

Analog-to-digital (ADC) and digital-to-analog (DAC) converters: types include flash, successive approximation (SAR), sigma-delta. Key metrics: resolution (bits), sampling rate, quantization error.

8. Logic Families

TTL vs CMOS: power, speed, noise margins, interfacing considerations. ECL for very high speed; CMOS for low power.

9. Programmable Logic

PLDs: PAL, GAL, CPLD, FPGA. Design flows use HDL (Verilog/VHDL), synthesis, place & route. Useful for prototyping and complex combinational/sequential logic.

10. Finite State Machines

Mealy vs Moore machines, state encoding, state minimization and state transition tables. Convert specifications to state diagrams and implement via flip-flops and logic.

11. Design Techniques & Tools

Use K‑maps and Boolean algebra for minimal logic. Prefer modular design and synchronous design practices.
Simulation: use ModelSim, Vivado, or other EDA tools. Synthesis constraints (timing) must be checked via static timing analysis.
Consider metastability and clock domain crossing when designing asynchronous interfaces.

12. Exam Tips

Practice K‑map simplification, timing diagram drawing, and designing small FSMs.
Memorize flip-flop characteristic tables and conversion between number systems.
Understand wiring and interfacing constraints for TTL/CMOS.

50 Practice MCQs

Correct options are highlighted when answers are shown.

Q1. Which gate implements the boolean function F = A · B?

A. AND gate

B. OR gate

C. XOR gate

D. NAND gate

Q2. De Morgan's theorem states that (A·B)' equals:

A. A' + B'

B. A' + B'

C. A' · B'

D. (A + B)'

Q3. A full adder adds:

A. Two bits only

B. Two bits and carry-in

C. Four bits

D. One bit and invert

Q4. Which device converts parallel data to serial data?

A. Parallel-in Serial-out (PISO) shift register

B. Serial-in Parallel-out (SIPO)

C. Register file

D. Encoder

Q5. Which flip-flop toggles its output when T = 1?

A. T flip-flop

B. D flip-flop

C. SR flip-flop

D. JK flip-flop

Q6. A Karnaugh map is used for:

A. Simplifying boolean expressions

B. Timing analysis

C. ADC conversion

D. Noise margin calculation

Q7. Which code has only one bit difference between successive values?

A. Gray code

B. Binary coded decimal

C. Two's complement

D. ASCII

Q8. The main advantage of CMOS over TTL is:

A. Lower static power consumption

B. Higher static power

C. Worse noise margin

D. Requires more power supply rails

Q9. What is the two's complement of binary 0101 (4-bit)?

A. 1010

B. 1111

C. 1011

D. 0101

Q10. A multiplexer selects one of many inputs using:

A. Select lines

B. Encoder output

C. Flip-flops

D. Clock signals

Q11. Which is a synchronous counter?

A. All flip-flops triggered by the same clock

B. Flip-flops triggered at different times

C. Only uses combinational logic

D. Counts asynchronously

Q12. Metastability in flip-flops is caused by:

A. Proper setup and hold times met

B. Violating setup or hold time during input change

C. Using edge-triggered flip-flops only

D. Using too many gates

Q13. Which device performs decimal to binary conversion automatically?

A. Encoder

B. Encoder (like decimal-to-binary encoder)

C. Decoder

D. Multiplexer

Q14. The propagation delay of a gate is the time from:

A. Input change to valid output change

B. Clock to output valid

C. Power-on to stable output

D. Setup to hold

Q15. Which flip-flop is easiest to implement with edge-triggered behavior using master-slave arrangement?

A. D flip-flop

B. SR flip-flop

C. T flip-flop

D. JK flip-flop

Q16. Which ADC type provides the fastest conversion at the cost of many comparators?

A. Flash ADC

B. SAR ADC

C. Sigma-delta ADC

D. Dual-slope ADC

Q17. Which logic gate is universal (can be used to build any other gate)?

A. NAND (or NOR)

B. XOR

C. XNOR

D. AND

Q18. Which is true about a ripple-carry adder?

A. Carry ripples through each full adder causing delay

B. No carry chain exists

C. It is the fastest adder

D. It uses lookup tables only

Q19. A decoder with n inputs can generate how many outputs?

A. n

B. 2^n

C. 2^n

D. n^2

Q20. Which HDL is commonly used for FPGA development along with Verilog?

A. VHDL

B. C

C. Python

D. Java

Q21. Which is an advantage of synchronous design over asynchronous design?

A. Easier timing verification and predictability

B. Always faster

C. Requires no clock

D. No metastability issues

Q22. Which of the following is NOT a valid ASCII code for a digit?

A. 0x30

B. 0x39

C. 0x3A

D. 0x38

Q23. Which flip-flop is asynchronous in response to S and R inputs?

A. SR latch (level-sensitive)

B. D flip-flop

C. T flip-flop

D. Edge-triggered JK

Q24. Which circuit detects overflow in two's complement addition?

A. XOR of carry into and out of MSB

B. XOR of carry into and out of MSB

C. AND of all bits

D. NOR of sign bits

Q25. Which device is used to store a single bit of data with clocked behavior?

A. D flip-flop

B. Latch

C. Multiplexer

D. Decoder

Q26. Which technique reduces glitch sensitivity in combinational circuits?

A. Proper hazard analysis and using consensus terms

B. Increasing clock frequency

C. Removing buffers

D. Using asynchronous resets only

Q27. Which representation is commonly used to simplify boolean functions by inspection?

A. Karnaugh map

B. State table

C. Timing diagram

D. RTL diagram

Q28. Which counter type uses feedback taps to create sequences like maximal length?

A. Linear Feedback Shift Register (LFSR)

B. Ring counter

C. Johnson counter

D. Binary ripple counter

Q29. Which is NOT a property of combinational circuits?

A. No memory

B. Output depends only on inputs

C. Contains flip-flops

D. Can be implemented with gates

Q30. A decoder is used in memory address decoding to:

A. Enable a single memory chip among many

B. Convert data to address

C. Add parity bits

D. Perform arithmetic

Q31. Which logic family typically offers the fastest switching?

A. ECL (Emitter-Coupled Logic)

B. TTL

C. CMOS

D. RTL

Q32. Which is used to prevent metastability when crossing clock domains?

A. Synchronizer (two-stage flip-flop)

B. Increase supply voltage

C. Use combinational logic only

D. Disable clocks

Q33. Which HDL construct describes concurrent hardware behavior?

A. Structural/Concurrent statements in Verilog/VHDL

B. For loop in software

C. Function call only

D. None of the above

Q34. Which device converts digital to analog voltage?

A. DAC

B. ADC

C. Comparator

D. Multiplexer

Q35. Which flip-flop characteristic table lists next-state as a function of present-state and inputs?

A. State transition table

B. Truth table for gates

C. K-map

D. Timing table

Q36. Which circuit is BEST suited for implementing combinational logic on an FPGA?

A. Look-Up Table (LUT)

B. Ripple-carry adder only

C. Discrete gates only

D. Analog multiplexer

Q37. Which is a non-volatile programmable device?

A. EEPROM-based PLD (e.g., some CPLDs)

B. SRAM FPGA without configuration memory

C. Volatile register file

D. Dynamic RAM

Q38. Which method is used to minimize states in a FSM?

A. State minimization (partitioning / equivalence classes)

B. Increasing flip-flops

C. Using more LUTs

D. Slowing clock

Q39. Which is true for a ripple counter's propagation delay as bit-width increases?

A. Delay increases linearly with number of bits

B. Delay remains constant

C. Delay decreases

D. Delay becomes random

Q40. Which is a benefit of synchronous reset over asynchronous reset?

A. Avoids reset-related metastability when released asynchronously

B. Faster reset assertion

C. Uses no clock

D. Removes need for flip-flops

Q41. Which technique reduces combinational path delay in adders?

A. Carry look-ahead or carry-select adders

B. Ripple-carry only

C. Using larger transistors only

D. Removing sum bits

Q42. Which is true about tri-state buffers?

A. They can disconnect output from the bus (high-Z) when disabled

B. Always drive the bus

C. Are used only in analog circuits

D. Replace flip-flops

Q43. Which approach helps meet timing closure in FPGA designs?

A. Pipelining and retiming

B. Removing registers

C. Increasing logic depth only

D. Using combinational loops

Q44. Which is an example of a combinational multiplier implementation?

A. Array multiplier (combinational)

B. Accumulator only

C. LFSR

D. Johnson counter

Q45. What does setup time mean for a flip-flop?

A. Minimum time input must be stable before clock edge

B. Time after clock edge input must change

C. Clock period minimum only

D. Propagation delay measure

Q46. Which is a common method to implement a priority encoder?

A. Use combinational logic that picks highest-priority input

B. Use sequential flip-flops only

C. Using ADCs

D. Using tri-state buses only

Q47. Which is true about CPLDs compared to FPGAs?

A. CPLDs have predictable timing and non-volatile configuration

B. CPLDs are always larger than FPGAs

C. FPGAs are non-volatile

D. CPLDs have no logic blocks

Q48. Which of the following is useful for glitch-free clock gating?

A. Use integrated clock gating cells or synchronized enable signals

B. Asynchronous resets only

C. Floating enable signals

D. Tri-state clocks

Q49. Which is the primary cause of dynamic power consumption in CMOS logic?

A. Charging and discharging capacitive loads (switching activity)

B. Leakage current only

C. Static power only

D. Inductive loads

Q50. Which is a good practice for FPGA floorplanning to improve performance?

A. Place related logic close and reduce long routing paths

B. Scatter logic randomly

C. Use no registers

D. Disable timing constraints