Microprocessors — Concise Notes

Comprehensive, exam-focused notes covering fundamentals, architecture (8085/8086 concepts), instruction sets, programming model, interrupts, memory interfacing, peripherals, and design tips.

1. Introduction

Microprocessor is a programmable integrated circuit that performs computation by executing instructions. It contains arithmetic/logic unit, control unit, registers, buses, and interfaces for memory and I/O.

2. Basic Architecture

Registers: general-purpose, accumulator, index registers, stack pointer (SP), program counter (PC), instruction register (IR).
Buses: Address bus (uni-directional), Data bus (bi-directional), Control bus (signals).
ALU and Flags: Zero, Sign, Carry, Parity/Overflow depending on CPU.

3. Classic Examples: 8085 & 8086 (concepts)

8085: 8-bit data bus, 16-bit address bus, simple interrupt structure. 8086: 16-bit external bus, segmented memory model, more complex instruction set and addressing modes.

4. Instruction Set & Addressing Modes

Instruction formats, opcodes, operands, addressing modes (immediate, direct, indirect, register, indexed, relative). Classification: data transfer, arithmetic, logical, branch, control instructions.

5. Assembly Language Programming

Writing small programs: load/store, arithmetic, looping, subroutines (CALL/RET), stack usage, interrupts and I/O. Understand assembler directives and macros.

6. Interrupts & Control

Interrupt types: hardware, software, vectored, non-vectored. Interrupt priorities, ISR (interrupt service routine), context saving and restoring, masking.

7. Memory & I/O Interfacing

Memory mapping (memory-mapped I/O vs port-mapped I/O), address decoding, interfacing RAM/ROM, wait states, bus contention and timing considerations.

8. Timing & Control Signals

Clock cycles, machine cycles, T-states (example 8085), control signals like ALE, RD, WR, IO/M, RESET, INTR/TRAP.

9. Peripherals & Programming

Common peripherals: timers/counters, UART/serial ports, parallel ports, ADC/DAC, programmable interrupt controllers, DMA controllers.

10. Modern Considerations

Microcontrollers vs microprocessors, pipelining, caches, MMU, multicore, power management, instruction set evolution (CISC→RISC), embedded systems design considerations.

11. Design Tips & Exam Advice

Practice assembly programs (loops, subroutines, stack operations).
Understand addressing modes and instruction timing for performance estimates.
Draw signal timing diagrams for bus cycles and interrupts.

50 Practice MCQs

Correct options are highlighted when answers are shown.

Q1. The program counter (PC) contains:

A. Current instruction's opcode

B. Address of next instruction

C. Stack top address

D. Interrupt vector

Q2. Which bus carries data between CPU and memory?

A. Data bus

B. Address bus

C. Control bus

D. Opcode bus

Q3. Which addressing mode uses the operand encoded within instruction?

A. Immediate

B. Direct

C. Indirect

D. Indexed

Q4. The instruction MOV A, B is an example of which type?

A. Data transfer

B. Arithmetic

C. Branch

D. Logical

Q5. An interrupt that cannot be masked is called:

A. Non-vectored

B. Non-maskable interrupt (NMI)

C. Maskable interrupt

D. Software interrupt

Q6. In 8085, ALE signal is used to:

A. Latch address from multiplexed bus

B. Indicate memory read

C. Reset the processor

D. Enable interrupts

Q7. Which register holds the status flags?

A. Flag register

B. Accumulator

C. Stack pointer

D. Instruction register

Q8. Which instruction transfers control unconditionally?

A. JMP

B. JZ

C. CALL

D. RET

Q9. Stack operates on which principle?

A. LIFO (Last-In, First-Out)

B. FIFO

C. Priority

D. Random

Q10. Which instruction returns from a subroutine?

A. RET

B. CALL

C. JMP

D. PUSH

Q11. What is the typical width of address bus in 8085?

A. 16 bits

B. 8 bits

C. 32 bits

D. 12 bits

Q12. Which instruction is used to call a subroutine?

A. CALL

B. RET

C. JMP

D. NOP

Q13. What does 'opcode' indicate?

A. Operation to perform

B. Operand value

C. Memory address

D. Flag state

Q14. Which instruction does nothing but consumes time?

A. NOP (No Operation)

B. HLT

C. JMP

D. MOV

Q15. Which register pair is commonly used as memory pointer in 8085?

A. HL pair

B. BC pair

C. DE pair

D. AF pair

Q16. A vectored interrupt provides:

A. Fixed address of ISR

B. No address information

C. Data payload

D. Priority only

Q17. Memory-mapped I/O maps devices to:

A. Memory address space

B. Separate I/O port space

C. Control bus only

D. Opcode space

Q18. Which instruction stores accumulator into memory?

A. STA addr

B. LDA addr

C. MOV A, M

D. INX H

Q19. What does 'HLT' do?

A. Halts the processor until reset or interrupt

B. Calls a subroutine

C. No operation

D. Restores flags

Q20. Which of the following is NOT a machine cycle in 8085?

A. Opcode fetch

B. Memory read

C. Interrupt mask

D. Memory write

Q21. What is the main difference between microprocessor and microcontroller?

A. Microcontroller integrates peripherals and memory on-chip

B. Microprocessor has on-chip peripherals by default

C. Microcontrollers are always faster

D. No difference

Q22. Which signal indicates a read operation to memory?

A. RD (Read)

B. WR

C. ALE

D. RESET

Q23. Which register stores the instruction currently being executed?

A. Instruction Register (IR)

B. Program Counter

C. Stack Pointer

D. Accumulator

Q24. How many bytes can a 16-bit address bus address?

A. 65536 bytes (64 KB)

B. 256 bytes

C. 4 GB

D. 32 KB

Q25. Which instruction increments HL register pair?

A. INX H

B. DAD H

C. INR H

D. DCX H

Q26. Which is used to expand memory decoding in address space?

A. Address decoder / demultiplexer

B. ALU

C. Flag register

D. Stack pointer

Q27. Which instruction is used to push data onto the stack?

A. PUSH

B. POP

C. XCHG

D. MOV

Q28. Which interrupt has the highest priority in 8085?

A. TRAP

B. RST7.5

C. INTR

D. RST5.5

Q29. Which instruction copies contents of one register to another?

A. MOV

B. MVI

C. STAX

D. LXI

Q30. Which instruction is used to load immediate data into register?

A. MVI

B. MOV

C. LDA

D. STA

Q31. Which of these is true about little-endian format?

A. Least significant byte stored at lowest address

B. Most significant byte at lowest address

C. Bytes are stored randomly

D. Only used in big systems

Q32. The instruction cycle consists of which main phases?

A. Fetch, Decode, Execute

B. Read, Write, Idle

C. Push, Pop, Jump

D. Load, Store, Reset

Q33. Which signal indicates an I/O operation in 8085?

A. IO/M (I/O or Memory)

B. RD

C. WR

D. RESET

Q34. Which instruction exchanges contents of H and D register pairs?

A. XCHG

B. EXX

C. SPHL

D. DAD

Q35. What is the function of the stack pointer (SP)?

A. Points to top of stack in memory

B. Holds program counter

C. Stores flags

D. Points to data register

Q36. Which addressing mode is useful for accessing array elements?

A. Indexed addressing

B. Immediate

C. Relative

D. Register direct

Q37. Which instruction decrements register pair HL?

A. DCX H

B. INX H

C. DCR H

D. INR H

Q38. Which is a non-vectored interrupt in 8085?

A. INTR

B. TRAP

C. RST7.5

D. RST6.5

Q39. Which instruction clears the carry flag?

A. CMC/CMC variant? (In 8085, CMC complements carry; for clear use: STC sets carry; to clear use CLC in some ISAs) — choose appropriate for teaching

B. STC

C. CMA

D. RLC

Q40. Which instruction rotates accumulator left through carry?

A. RAL

B. RLC

C. RAR

D. RRC

Q41. Which of the following stores a 16-bit immediate value into register pair?

A. LXI rp, data16

B. MVI

C. MOV

D. INX

Q42. Which instruction tests a bit in accumulator?

A. BIT (in some ISAs) or CMA? (Use BIT-like instruction concept)

B. ORA

C. ANA

D. MOV

Q43. Which instruction sets the carry flag?

A. STC

B. CMC

C. CMA

D. RAR

Q44. Which addressing mode uses the program counter to compute target address?

A. Relative addressing

B. Immediate

C. Indirect

D. Indexed

Q45. Which instruction copies the top of stack to register pair HL?

A. SPHL (Stack Pointer to HL) — if available; otherwise use POP H as appropriate

B. PUSH H

C. POP H

D. XTHL

Q46. What is the effect of executing DI (Disable Interrupts)?

A. Masks (disables) maskable interrupts

B. Clears all flags

C. Halts the processor

D. Resets the stack pointer

Q47. Which instruction exchanges the top two bytes on the stack with HL register?

A. XTHL

B. SPHL

C. PUSH H

D. POP H

Q48. Which mechanism speeds up instruction fetch in modern processors?

A. Instruction cache (I-cache)

B. Larger register file only

C. Slower clock

D. ROM only

Q49. Which technique is used to reduce instruction execution latency by predicting branches?

A. Branch prediction

B. Caching only

C. Interrupt masking

D. DMA

Q50. Which is true about memory segmentation (like 8086)?

A. It allows addressing larger memory via segment:offset pairs

B. Removes need for offsets

C. Is identical to paging

D. Always prevents fragmentation